EEPROM with split gate source side injection with sidewall spacers

ABSTRACT

Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. Ser. No.08/193,707 filed Feb. 9, 1994, which in turn is a divisional of U.S.Ser. No. 07/820,364, filed Jan. 14, 1992, now U.S. Pat. No. 5,313,421issued May 17, 1994.

TECHNICAL FIELD

[0002] This invention pertains to semiconductor memory cells and arrays,more particularly to electrically erasable programmable read onlymemories.

BACKGROUND

[0003] Erasable programmable read only memories (EPROMs) andelectrically erasable programmable read only (EEPROMs) are well known inthe art. These devices have the ability to store data in non-volatilefashion, while also being capable of being erased and rewritten asdesired. EPROM devices are typically erased by exposing the integratedcircuit device to ultraviolet radiation, while EEPROMs allow erasure tobe performed electrically.

[0004] One form of EEPROM device includes a so-called “split-gate”electrode, in which the control gate includes a first portion overlayinga floating gate and a second portion directly overlaying the channel.Such a split gate structure is described in a 5-Volt-OnlyFast-Programmable Flash EEPROM Cell with a Double Polysilicon Split-GateStructure by J. Van Houdt et al, Eleventh IEEE Non-VolatileSemiconductor Workshop, February 1991, in which charge is injected intothe floating gate from the source side of the cell. U.S. Pat. No.4,652,897 describes an EEPROM device which does not utilize asplit-gate, but which also provides injection to the floating gate fromthe source side of the device.

[0005] As described in the above referenced U.S. Pat. No. 4,652,897,memory cells are typically arranged in an array, as is well known in theart. One form of such an array utilizes buried diffusions, in whichsource and array regions are covered with a fairly thick layer ofinsulating material. This is shown for example, in U.S. Pat. Nos.4,151,020; 4,151,021; 4,184,207; and 4,271,421. Such buried diffusiondevices often utilize a virtual ground approach, in which columnsconnecting the sources of a first column of memory cells also serves toconnect drains of an adjacent column of memory cells.

[0006] While many EEPROM devices utilize two layers of polycrystallinesilicon, one for the formation of the floating gate, and the other forthe formation of the control gate and possibly electrical interconnects,other EEPROM devices utilize three layers of polycrystalline silicon.For example, U.S. Pat. No. 4,302,766 provides a first polycrystallinesilicon layer for the floating gate, a second polycrystalline siliconlayer for the control gate, and a third polycrystalline silicon layercoupled through an erase window to a portion of the firstpolycrystalline silicon layer for use during erasure of the cell. U.S.Pat. No. 4,331,968 also uses a third layer of polycrystalline silicon toform an erase gate, while U.S. Pat. No. 4,462,090 forms an addressinggate electrode utilizing a third layer of polycrystalline silicon. U.S.Pat. Nos. 4,561,004 and 4,803,529 also use three layers ofpolycrystalline silicon in their own specific configurations.

[0007] Japanese Patent Publication 61-181168 appears to utilize threelayers of polycrystalline silicon to provide additional capacitivecoupling to the floating gate. Japanese Patent Publication 63-265391appears to pertain to a buried diffusion array, possibly utilizingvirtual grounds.

[0008] European Patent Application 0373830 describes an EEPROM in whichtwo polycrystalline silicon layers are used, with the second layer ofpolycrystalline silicon having two pieces, one of which provides theerase function, and one of which provides the steering function.

[0009] “A New Flash-Erase EEPROM Cell With a Sidewall Select-Gate on itsSource Side” by K. Naruke et al. IEDM-89-603 and U.S. Pat. No. 4,794,565describe an EEPROM utilizing a side wall select gate located on thesource side of the field effect transistor.

[0010] “EPROM Cell With High Gate Injection Efficiency” by M. Kamiya etal. IEDM 82-741, and U.S. Pat. No. 4,622,656 describe an EEPROM devicein which a reduced programming voltage is provided by having a highlydoped channel region under the select gate, and the channel region underthe floating gate being either lightly doped or doped to the oppositeconductivity type, thereby providing a significant surface potential gapat the transition location of the channel.

[0011] In recent years there has been significant interest in producinghigh capacity FLASH memory devices which use split-gate, source-side hotelectron programming, in place of the more conventional drain-sidechannel hot electron (CHE) mechanism.

[0012] The reasons for this include its inherently lower write powerrequirement ({fraction (1/10)}th that of CHE or less), facilitating lowvoltage operation and higher write speeds via increased parallelism. Inaddition, the split gate structure is not susceptible to “overerase”related problems (a problem for single gate FLASH memories such asETOX), and does not experience programming difficulty due to strongovererase, which can hinder programming after an erasure operation insplit-gate CHE programming devices.

[0013] In view of these benefits, sundisk Corporation has patente FLASHmemory cell and array variants which use source side injectionintegrated with SunDisk's proprietary thick oxide, poly-to-poly erasetunneling technology, to make a highly scalable, reliable, low powerprogramming cell (D.C. Guterman, G. Sanachiasa, Y. Fong and E. Harari,U.S. Pat. No. 5 5,313,421).

[0014] The concept of a multi-bit storage non-volatile cell using asplit gate structure was described by G. S. Alberts and H. N. Kotecha(Multi-bit storage FET EAROM cell, IBM Technical Disclosure Bulletin,Vol. 24 No. 7A, p. 3311, December 1981). They describe a two-poly, threetransistor element-in-series cell, in which the center transistor'schannel is controlled directly by the poly2 control gate (which alsoserves as the cell select gate), and each of the two end transistorchannels are controlled by corresponding poly1 floating gates, which inturn are capacitively coupled to the control gate, thereby realizing aplurality of bits in the one physical cell structure.

[0015] Recently, at the 1994 IEDM, Bright Microelectronics along withHyundai presented a similar dual-bit split-gate cell, integrated into acontactless, virtual ground array, and using source side injectionprogramming (Y. Y. Ma and K. Chang, U.S. Pat. No. 5,278,439—referred tohenceforth as the Ma approach). One structural difference here from theIBM approach is their separation of the capacitively coupling controlgates, which are formed in poly2, and the select gate, which is formedin poly3.

[0016] In the Ma approach, they use “conventional” negative control gatedriven tunneling through an ultra-thin poly1 gate oxide (about 100 Å orless). This erase approach poses some serious limitations. Erase of oneof the two storage transistors uses floating gate to drain tunnelingthrough the ultra-thin oxide, accomplished by biasing the drain to 7 vand corresponding control gate to −10 v. Because both of these lines runperpendicular to the select gate, this forces a block of cells which areto be simultaneously erased (e.g. a sector) to be bit line oriented, asopposed to the more conventional word line (select gate) oriented block;i.e. its sector must be column organized and thus it cannot be roworganized. (For example, a sector could be two columns of floating gatesstraddling a bit line/diffusion, including the right hand floating gatesof the left side cells' floating gate pair plus the left hand floatinggates of the right side cells.) This leads to the followingdisadvantages in the Ma implementation:

[0017] (1) Limited to column sector architecture; i.e. cannot readilysupport the higher read performance row oriented sector architecture.(Since here, within a sector, both erase anode and corresponding controlgates run perpendicular to row line direction, this precludes themassively parallel “chunk” implementation of the row oriented sector,which can simultaneously access large numbers of cells within thatsector).

[0018] (2) Requires ultra-thin, approximately 100 Å, tunneling oxide,imposing following limitations:

[0019] Scaling limitation associated with pushing the limits of usableoxide thicknesses, plus the additional area needs associated withmaintaining adequate coupling requirements, which must combat theinherently high capacitance per unit area of such a thin oxide;

[0020] A myriad of potential retention/reliability problems inherent tousing ultra-thin oxide, combined with the parasitic band-to-bandtunneling/hole injection associated with the high substrate fieldsadjacent to the diffusion anode; and

[0021] Negative gate bias requirements on control gate, to limitband-to-band injection problems, impose process and circuit complexity,plus potentially more layout area requirement.

SUMMARY OF THE INVENTION

[0022] In accordance with the teachings of this invention, novel memorycells are described utilizing source-side injection. Source-sideinjection allows programming utilizing very small programming currents.If desired, in accordance with the teachings of this invention,to-be-programmed cells along a column are programmed simultaneouslywhich, due to the small programming current required for each cell, doesnot require an unacceptably large programming current for any givenprogramming operation. In one embodiment of this invention, the memoryarrays are organized in sectors with each sector being formed of asingle column or a group of columns having their control gates connectedin common. In one embodiment, a high speed shift register is used inplace of a row decoder in order to serially shift in the data for theword lines, with all of the data for each word line of a sector beingcontained in the shift register on completion of its serial loading. Inone embodiment, additional speed is achieved by utilizing a parallelloaded buffer register which receives data in parallel from the highspeed shift register and holds that data during the write operation,allowing the shift register to receive serial loaded data during thewrite operation for use in a subsequent write operation. In oneembodiment, a verification is performed in parallel on allto-be-programmed cells in a column and the bit line current monitored.If all of the to-be-programmed cells have been properly programmed, thebit line current will be substantially zero. If bit line current isdetected, another write operation is performed on all cells of thesector, and another verify operation is performed. This write/verifyprocedure is repeated until verification is successful, as detected bysubstantially zero bit line current.

[0023] Among the objectives of the novel cells constructed in accordancewith this invention are avoidance of programming limitations such as:

[0024] 1. High Channel Currents (Power) required for Programming.

[0025] 2. High Drain Voltage Requirements, which increase with increasedlevels of erasure.

[0026] 3. Loss of Read Performance associated with an increase inProgramming Efficiency via Heavy Channel doping.

[0027] 4. Program Wearout Associated with Maintaining a High Drain Biason Cells exposed to this bias, including both those cells targeted forprogramming and those cells not targeted but still exposed to thevoltage.

[0028] In an alternative embodiment of this invention, a multi-bitmemory cell is taught utilizing a 3-poly, 3 transistor element-in-seriescell in which the center transistor's channel is controlled directly bythe poly 3 control gate (which serves as both a cell select gate anderase anode) and each of the two end transistor channels are controlledby corresponding poly1 floating gates, which in turn are capacitivelycoupled to the poly 2 control or steering gates, thereby realizing aplurality of bits in the one physical cell structure.

[0029] The multi-bit cell contains two bits per unit memory cell, comingfrom two floating gate portions, each having their own control gate(which, in the virtual ground array, runs parallel to the bits lines),and sharing one select gate, placed physically between them (which, inthe virtual ground array, runs perpendicular to the bit lines). Thediffusion BN+ source/drains straddle the two floating gates, on theiropposite facing channel edges to those adjacent the select gate/transferchannel.

[0030] Unlike a single floating gate cell, because here the two floatingchannels lie in a series configuration, the programmed threshold voltagelevel of each floating gate must be limited in its upper value in orderto be readable (similarly to the Toshiba NAND cell). In this way, eitherfloating gate channel can be unconditionally turned on (i.e. independentof its stored state) when appropriate bias is applied to itscorresponding control gate, when reading the state of the other floatinggate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIGS. 1a, 1 b, and 1 c, are cell layout, cross-sectional diagram,and equivalent circuit schematic of one embodiment of this invention;

[0032]FIG. 1d is a plan view of one embodiment of an array consisting ofa plurality of cells of FIGS. 1a-1 c;

[0033]FIG. 1e is a block diagram depicting a memory array organized bysectors, with appropriate control circuitry;

[0034]FIG. 1f depicts the operation of one embodiment of a memory arrayorganized by sectors as shown in FIG. 1e;

[0035]FIG. 1g is a plan view depicting an alternative array embodimentutilizing cells depicted in FIGS. 1a-1 c;

[0036]FIG. 2a is a cross-sectional view depicting an alternativeembodiment of this invention similar that of FIG. 1b;

[0037]FIG. 2b is a plan view of one embodiment of an array of memorycells constructed utilizing cells depicted in the cross-sectional viewof FIG. 2a;

[0038]FIG. 2c is a diagram depicting the organization and operatingcondition of an array such as that of FIG. 2b;

[0039]FIG. 3 is a graph depicting the operation of a memory cell of FIG.1b;

[0040]FIG. 4 depicts the electrical field distribution along channels ofthe device of FIG. 5;

[0041]FIG. 5 is a cross-sectional view one embodiment of a 2-poly cellof this invention;

[0042]FIG. 6 is a cross-sectional view of another embodiment of a 2-polycell of this invention;

[0043]FIG. 7a is a plan view depicting a portion of a process sequenceutilized in accordance with one embodiment of this invention;

[0044]FIG. 7b is a cross-sectional view of the embodiment shown in theplan view of FIG. 7a;

[0045]FIG. 8 is a cross-sectional view depicting a fabrication stepsuitable for use in accordance with the teachings of this invention;

[0046]FIGS. 9a and 9 b are top and cross-sectional views, respectivelyof one embodiment of a multiple-bit memory cell structure of thisinvention;

[0047]FIG. 10a is a schematic diagram of one multi-bit cell of thisinvention;

[0048]FIG. 10b is a circuit diagram depicting one embodiment of an arrayof multiple-bit memory cells of this invention, such as those of FIGS.9A and 9B;

[0049]FIG. 10c is a circuit diagram depicting one embodiment of an arrayof cells as shown in FIG. 10b plus segment decode transistor matrix forboth bit lines and steering lines;

[0050]FIGS. 11a through 11 e are detailed top and cross-sectional views;and

[0051]FIGS. 12a-12 f are cross sectional views depicting fabricationsteps suitable for use in fabricating multi-bit memory cells inaccordance with this invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

[0052] The cell layout, cross-sectional diagram and equivalent circuitschematic of one embodiment are shown in FIGS. 1a, 1 b, and 1 c,respectively. Similar reference numerals have been used in FIGS. 1a, 1b, and 1 c. Referring to the cross-sectional view of FIG. 1b, thisembodiment of the novel EEPROM cell, 101 of this invention includes aburied source region 102 and a buried drain region 103, each beingburied by a relatively thick layer of dielectric 104 and 105,respectively. Channel region 106 is divided into two portions, a firstportion 106-1 which is influenced by the third layer polycrystallinesilicon 109 and which forms a select gate, and a second portion 106-2which is influenced by floating gate 107 formed of a first layer ofpolycrystalline silicon and which, in turn, is influenced by controlgate 108 formed of a second layer polycrystalline silicon. As is wellknown in the art, suitable dielectric layers such as thermally grownoxide are located between channel 106 and polycrystalline silicon layer109 and polycrystalline silicon layer 107. Similarly, suitabledielectric layers such as oxide or composite oxide/nitride are formedbetween the three layers of polycrystalline silicon. Polycrystallinemetal silicide can be used in place of one or more of thepolycrystalline silicon layers 108 and 109. If desired, a highly-dopedP+ region 120 is used within channel 106-2 adjacent buried drain region103. This region 120 is formed, for example, as a double diffused MOS(DMOS) region in order to establish the threshold voltage V_(t) of thememory transistor including channel 106-2. This helps to provide astable threshold voltage, even though the amount of charges trapped inthe gate oxide layer in the vicinity of the gap between 106-1 and 106-2tends to increase with a large number of programming cycles.

[0053] An example of operating conditions and levels associated with theembodiment of FIG. 1b are shown in Table 1. High efficiency programmingcomes about by the ability to simultaneously create a high field regionin channel 106-2 under the floating gate, which under the biasconditions of Table 1 occur near the gap between channels 106-1 and106-2 (see above mentioned IEDM article of Kamiya for theory) whilemaintaining a low channel/current. Since this high field causes electroninjection to floating gate 107 near the source side of channel 106-2,this type of operation is termed “source-side” injection. This mechanismprovides high efficiency, low power programming by maintaining a lowchannel current via word line 109 throttling by using a bias operatingnear channel threshold, VT_(p3). A major attribute of this type ofoperation is that it allows for a high drive condition in floating gatechannel 106-2 under the floating gate (in fact it thrives on it),offering high-performance read, without degrading programmingperformance. This is because the very weak drive condition on the selecttransistor of channel 106-1 is established via the throttling mentionedabove to achieve the high fields in the vicinity of the poly 3/poly 1gap. These fields accelerate the electrons to sufficiently energeticlevels (i.e. >3.1 eV) to surmount the Si/SiO₂ interface barrier at thesource side of floating gate 107. Furthermore, there is a significantvertical component to that field (i.e. normal to the Si/SiO₂ surface)driving the electrons up to the surface of channel 106, and therebyassisting the injection into floating gate 107. No read performancepenalty is incurred to establish this high field condition. This is instark contrast to conventional drain side programming, wherein efficientprogram requires strong channel saturation which shuns high floatinggate channel drives, strong overerase, or a weakly turned on seriesselect transistor. These problems with drain side programming dictatehigh channel currents, care in overerase, potentially high drainvoltages, and unfavorable fields (potentially subducting the channelbelow the surface at the drain side and driving electrons downward awayfrom the floating gate).

[0054] Consequently, in accordance with the teachings of this invention,programming efficiencies (T_(G)/T_(D)) ranging from 10⁻⁵ to 10⁻3 arepossible, with in the range of 1 mA during programming, which is two tothree orders of magnitude smaller than conventional drain sideprogramming. This offers the potential for very fast system levelprogramming by allowing the programming of 100 times as many memorycells in parallel, thereby achieving a 100 fold increase in effectiveprogram speed compared with prior art drain side programming. TABLE 1State Table & Operating Conditions (FIG. 1b) Poly 3 Poly 2 Drain SourceNode (Word (Steering (BN & & (BN Operation line) Gate) Drain) Source)READ RELATED STANDBY 0v 0v 1.0v or 1.0v or 0v 0v READ SELECTED 5v 0v1.0v or 0v or 0v 1.0v READ UNSELECTED 5v 0v 1.0v 1.0v ERASE RELATEDERASE UNSELECTED 5v 0v 0v 0v ERASE Option 1 5v −10to−17v 0v 0v or Option2 12-22v 0v 0v 0v PROGRAM RELATED PROGRAM H1.5v 14-20v 5-7v 0v SELECTEDPROGRAM 0v 14-20v 5-7v 0v UNSELECTED H1.5V 14-20v 5-7v 5-7v 0v 14-20v 0v0v

[0055] A major feature of the cell of this invention is the decouplingof the select function (in this case poly 3 select transistor 110 inFIG. 1b) from the steering function (poly 2 control gate 108). Duringprogramming, this allows the independent control of cell selection/draincurrent throttling via poly 3 word line 109 bias (biased at slightlyhigher than VT_(p3)) and strong positive voltage coupling onto floatinggate 107 (by raising poly 2 control gate 108 to a high voltage, such asabout 12 volts). Also, in accordance with the teachings of thisinvention, the drain voltage can be adjusted independently of steeringand select transistor voltage levels, to optimize programming.

[0056] During read, the decoupling feature of this invention providestwo important advantages, and one exciting side benefit.

[0057] 1. The ability to set control gate 108 at the optimum voltagelevel for memory state sensing, i.e. the best balanced reference pointfor both programmed and erased states. This independence is in contrastto conventional cells wherein the control gate also serves as the selecttransistor, dictating a voltage level consistent with selection (e.g.Vcc=5 v+⁻10%).

[0058] 2. Improved margin by virtue of being a fixed, (potentiallyregulated) reference voltage, eliminating the Vcc variation of +⁻10%inherent to the word line bias levels. (This alone could improve thefloating gate memory window by about 0.6 v).

[0059] 3. A side benefit of the ability to independently set the controlgate voltage bias discussed above, offers the possibility of a simpleway for re-referencing the memory cell for multi-state (i.e. more thanconventional 2-state) encoded data. For example if the cell is encodedinto three level states, (such as logical 1=strongly erased/highconducting, logical 2=partially programmed/weakly conducting; logical3=strongly programmed,) then the control gate voltage can be set at twodifferent levels in a two pass read scheme. For example, in the firstpass read the control gate voltage would be set at about ov todiscriminate between the logical 1 state and the logical 2/logical 3states. In the second pass read the control/gate voltage is set to about2 v, to discriminate between the logical 3 state and the logical1/logical 2 states. By combining the information of this two pass read(e.g. according to Table 2) the original state of the 3 state cell isrecovered. This biasing can be done independently of sense amp referencecell considerations allowing a single sense amp/reference cell circuitto detect the different states via a multi-pass read scheme. TABLE 2READ PASS 1 PASS 2 STATE [Ref. = 0v] [Ref. = 2] 1 Hi Hi 2 Lo Hi 3 Lo Lo

[0060] The two options for erase operation/bias conditions shown inTable 1 stem from two different sets of considerations. The first optionshown brings poly 2 control gate 108 to a large negative voltage, butallows poly 3 word line 109 to remain at a low voltage (e.g. 0 v to 5v). This is desirable since the word lines and their decoders arepreferably high performance, and repeated many times with a tightlypitched requirement, making high voltage word line requirements moredifficult and real estate consuming to implement. Poly 2 control orsteering gate 108 on the other hand could be common to a multiplicity ofword lines (e.g. a sector consisting of 4 or more word lines), puttingless demands on real estate and minimal impact to performance. Possibledrawbacks of this approach are the process and device requirements tosupport both negative as well as positive polarity high voltagecircuitry, and reduced steering effectiveness in that the channel cannotassist in steering by virtue of it being held at or near ground (i.e.can't go to large negative potential).

[0061] Note that poly 2 is used only as a steering electrode during allthree operations. Poly 3, which is the word line connection to theX-decoder, only sees 0V to 5V (other than for erase option 2), and itscapacitance can be made relatively small. It is relatively easy togenerate +5V and −17V on poly 2 since both writing and erasing are slowoperations relative to reading and there is no DC current drain. The−17V does require high voltage PMOS in the erase decode, but the +5V onpoly 3 aids in reducing the maximum negative voltage required on poly 2during erase.

[0062] The second option of using high word line voltage bias for eraseeliminates both of the above potential drawbacks, but burdens the highperformance, tightly pitched word line/driver with high voltagerequirement.

[0063]FIG. 1d is a plan view of one embodiment of an array consisting ofa plurality of cells constructed as just described with respect to FIGS.1a-1 c, and using similar reference numerals. Also shown, are channelstop isolation regions 180.

[0064]FIG. 1e shows a block diagram of a memory array similar to thatshown in the plan view of FIG. 1d which is organized by sectors, withappropriate control circuitry. Operation of one embodiment of such amemory array organized by sectors is shown in FIG. 1f, where theabbreviations used have the following meanings:

[0065] FLT=float

[0066] V_(BE)=bit line erase voltage

[0067] V_(WE)=word line erase voltage

[0068] DI=data in

[0069] DIV=data in during verify operation

[0070] V_(CEU)=control gate erase voltage—unselected

[0071] V_(CE)=control gate erase voltage—selected

[0072] S.A.=sense amplifier

[0073] V_(CM)=control gate margin voltage (during verify operation)

[0074] V_(CP)=control gate program voltage

[0075] V_(CR)=control gate read voltage

[0076] V_(CE)=control gate erase voltage

[0077] As shown in FIGS. 1e and 1 f, in this embodiment sectors areformed by a single column or a group of columns having their controlgate connected in common. This allows a high speed shift register to beused in place of a row decoder in order to serially shift in a wholeblock of column data for the word lines, with the data for each wordline being contained in the shift register on completion of its serialloading. The use of such a high speed shift register saves circuit areaon an integrated circuit by serving both encoding and latching functionsnormally performed by a row decoder. Furthermore, speed is improved byincluding a parallel loaded buffer register which receives data inparallel from the high speed shift register and holds that data duringthe write operation. While the write operation takes place based uponthe data stored in the buffer register, the high speed serial shiftregister receives the next block of data for subsequent transfer to thebuffer register for the next write operation. In one embodiment of thisinvention, each sector has an associated latch for tagging that sectorin preparation for an erase of a plurality of tagged sectors.

[0078] In one embodiment of this invention, a sector is formed in agroup of four cell columns, each column being 1024 bits tall with acommon control gate and an associated sector latch. In this embodiment,verification of programming is performed in parallel on allto-be-programmed cells in a single column. Logical 0 state cells haveword lines at 0 volts while logical 1 state cells have word lines at apositive voltage, such as 5 volts. The control gate and drain voltagesare reduced to a verify level to allow for proper margin testing and thebit line current is monitored. If all of the to-be-programmed cells havebeen properly programmed, the bit line current will be 0 orsubstantially so. If not, it is known that one or more of theto-be-programmed cells in the column have not been properly programmed,and another write operation is performed on the entire column, therebyassuring that any incompletely ones of the to-be-written cells are againwritten. An additional verify step is performed to verify that thecolumn has been properly programmed.

[0079] One embodiment of a process suitable for fabricating thestructure having the cross-sectional view of FIG. 1b is now described.This embodiment can be implemented in a very small area with no need foran isoplanar oxide when utilizing a virtual ground, allowing anisolation implant to be placed in the remaining field which is notcovered by diffusions or polycrystalline silicon and avoidssusceptibility to substrate pitting associated with the SAMOS etch inthe field isolation region not covered by poly 1. This is achieved, forexample, with the following process sequence:

[0080] 1. Form BN⁺ bit lines in vertical strips. Grow approximately 1500Å oxide on top of BN⁺, and approximately 200-300 Å gate oxide.

[0081] 2. As shown in FIGS. 7a and 7 b, deposit poly 1 to a suitableconductance and etch in horizontal strips perpendicular to the BN⁺diffusion. Fill the spaces between adjacent strips of poly 1 withdeposited oxide, such as CVD followed by an etch back. This approachprotects the field isolation regions, and if desired it can be precededby a boron channel stop implant.

[0082] An alternative for steps 1 and 2 of the above process sequence isforming horizontal strips of isolation oxide first, and then depositingP₁ and etched back in RIE to fill and planarize the horizontal groovesbetween adjacent strips of isolation oxide.

[0083] 3. Form thin dielectric 140 such as ONO of approximately 300-400Å. covering poly 1 strips.

[0084] 4. Deposit poly 2 and form a suitably thick dielectric overlayer(e.g., approximately 2000-3000 Å of CVD densified oxide). Etch thisoxide and underlying poly 2 in long vertical strips parallel to bit line(BN⁺) diffusions.

[0085] 5. Form oxide spacers 62 along edges of poly 2 and use edge ofthese spacers to define the floating gate by etching off exposed poly 1(i.e. poly 1 not covered by poly 2 or by spacer).

[0086] 6. Form tunnel erase oxide in a conventional manner, as describedin U.S. patent application Ser. No. 323,779, filed Mar. 15, 1989, overexposed edges of poly 1 as well as gate oxide over the channel of theselect transistor (channel 106-1 in FIG. 1b).

[0087] 7. Deposit poly 3 or polysilicide, and form word lines inhorizontal strips.

[0088] Another embodiment for achieving a virtual ground cell withoutthe use of the buried diffusion formed early in the process is nowdescribed. In place of the BN+ of step 1, after step 6 a photoresist(PR) masked arsenic source/drain implant 103 a is used, self-aligned toone edge of poly 2 108 after poly 1 107 stack formation but leaving anunimplanted region along the other edge to become the poly 3 controlledselect transistor channel (see FIG. 8). The isolation oxide thicknessformed earlier between poly 1 strips is made sufficiently thick towithstand the self-aligned poly 2/1 stack etch without exposing thesubstrate to pitting, but thin enough such that following this stacketch it is readily removed to expose the substrate to the source drainimplant. This offers the benefit of reduced thermal drive of the arsenicjunction laterally facilitating scaling. The remainder of the processsteps of this embodiment follows the prior embodiment.

[0089] In summary, the novel cell of this invention offers the followingbenefits.

[0090] Very low programming current.

[0091] Low programming drain voltage requirement/eliminating the needfor high voltage.

[0092] Immunity of Programmability to increased levels of erase.

[0093] Adjustability of memory state for optimum read of both programand erased states.

[0094] Improved margin by elimination of sensitivity to ±10% Vccvariation on the steering element.

[0095] Potential for pure low voltage word line/decoder implementation.

[0096] Facilitates multi-state cell sensing.

[0097] Reduced susceptibility to source side hot-electron programminginduced trapping by establishing a separate threshold control region atthe drain.

[0098] A second array embodiment is similar to that of FIG. 1d but usesthe cell embodiment shown in FIG. 1b, to form a row oriented sectorarchitecture, is shown in FIG. 1g. A sector consists of a group of rows,four in this example, which are erased together. Erase uses option 2 ofTable 1, for this row oriented sector architecture, bringing all thepoly 3 word lines of a sector to high voltage. The poly 2 steering gateis common to a group of N sectors where N can range from 1 to the fullsize of the memory array. Similarly the BN+ columns can alternativelycontinuously span the full length of the array or be broken down into acollection of shorter length, local columns. These connect to a global(full array length) column through a select transistor driven by anadditional level of decoding. The local columns can range from 1 to Nsectors. The preferred embodiment is to have local columns span the samenumber of sectors as the poly 2 steering gate. A preferred number ofsectors, N, spanned by local columns and poly 2 steering is around 8.This is because if N is much smaller than 8, the area overhead for localcolumn section devices and poly 2 steering gate routing is high inrelation to the area of arrayed cells, while if N is much larger than 8,the benefits of having localized columns and poly 2 steering diminish.These benefits are: (1) reduced bit line capacitance improving readperformance; (2) reduced repetitive exposure on unselected sectors tothe raised voltage conditions on drains and steering electrodes whenprogramming one sector within the N-sector group, and associatedpotential disturb phenomena; and (3) increased confinement of arrayrelated failures thereby increasing the efficiency of replacing suchfailures. Read, program and unselected conditions are as described inTable 1, during read or program. The poly 3 word line in the selectedrow within the selected sector is turned on, 5 volts for read andapproximately 1 volt for programming. Concurrently, the drain to sourcebias conditions are applied to the columns, approximately 5 volts forprogram and approximately 1.0-1.5 volts for read. In one embodiment,alternate bits in a selected row are programmed simultaneously, therebypermitting all bits in a selected row to be programmed utilizing twoprogramming operations. In a similar manner, in this alternativeembodiment, alternate bits in a selected row are read (or verified)simultaneously, thereby permitting all bits in a selected row to be read(or verified) utilizing two read (or verify) operations. After one rowin the sector has finished reading or writing, the next row is selected,and so forth to the end of the sector. The resulting row oriented sectorarchitecture and array operation is much more conventional than thecolumn oriented sector of the first embodiment, and consequentlyoperates in a more traditional manner. Both embodiments share theintrinsic low power capability of this invention, but the row orientedsector embodiment requires, in addition, a full complement of dataregisters to support massively parallel write and verify features.

[0099]FIG. 2a shows an alternative array embodiment of this inventionwhich does not utilize buried diffusion regions. Thus, source region 102and drain region 103 are formed in a conventional manner and not buriedby a thick dielectric layer as is the case in the embodiment of FIG. 1b.A plurality of memory cells are shown in FIG. 2a along a cross sectionof a typical array structure, with elements of one such cell numberedusing reference numerals corresponding to similar structure in FIG. 1b.Table 3 depicts an example of the operating conditions appropriate forthe embodiment of FIG. 2a. This a more traditional cell approachcompared to the buried diffusion cell, with source/drain diffusionsformed after all the polycrystalline silicon structures are formed. Itrequires one drain contact to metal bit line for every 2 cells, makingit approximately 30% to 50% larger than the buried diffusion cell withsimilar layout rules. In all other respects, this alternative embodimentoffers the same benefits as listed above for the buried diffusionembodiment of FIG. 1b.

[0100]FIG. 2b is a plan view of one embodiment of an array of memorycells constructed as described above with reference to FIG. 2a.

[0101]FIG. 2c is an equivalent circuit diagram depicting theorganization of such a memory array in sectors, with appropriateoperating conditions and voltages shown. The preferred embodiment for asector organized array uses two word lines which straddle a source lineas part of a sector, along with their associated poly 2 steering gatesand source line. A full sector consists of some multiple of such pairing(e.g. 2 such pairs or 4 word lines, each word line containing 128 bytesand overhead cells, and straddling two source lines, constitute onesector).

[0102] As shown in the embodiment of FIG. 2c, the steering lines areconnected together within a sector as are the source lines (i.e. asector which consists of row lines grouped together respectively anddriven by common drivers). The embodiment described here confines thewrite operation to the sector being written to, while the bit line biasconditions (2.5 v during read and approximately 5 v possible duringwrite) are non-disturbing to the cells because the bias is applied tothe select transistor side of the cell and not to the floating gateside. In a two state cell, to write the cell to a logical one, the bitline is held at zero volts, causing the cell to program via source-sideinjection. Conversely, to inhibit writing, the bit line is held high(typically about 5 volts), thereby cutting off the channel, leaving thecell in the erased state.

[0103] Sector erase takes place by tagging the selected sector andraising the associated row lines to a sufficiently high voltage to erasethe floating gates to their required erased levels.

[0104] Because of the low programming currents associated with sourceside injection (approximately 1-5 microamps/cell), massive parallelprogramming is made practical, e.g. a full row line of approximately1000 cells is programmed in a single operation with total current lessthan approximately 1-5 mA, thus providing more than 100 times moreefficiency than prior art drain side programming arrays. TABLE 3 StateTable & Operating Conditions (FIG. 2a) Poly 3 Poly 2 Node (Word(Steering Operation line) Gate) Drain Source READ RELATED STANDBY 0v 0vDon't care 0v READ SELECTED 5v 0v 2.5v 0v READ UNSELECTED 5v 0v Don'tcare 0v ERASE RELATED STANDBY 0v 0v 0v 0v ERASE Option 1 12v-22v 0v 0v0v or Option 2 5v −10v to 0v 0v −12v PROGRAM RELATED PROGRAM H1.0v 14-200v 5v-8v SELECTED PROGRAM 0v 14-20 0v 5v-8v UNSELECTED H1.0v 14-20 5v5v-8v 0v 14-20 5v 5v-8v

[0105]FIG. 3 is a graph depicting the gate current into poly 1 gate 107of FIG. 1b (which is not floating in the FIG. 3 test device to allowthis measurement to be made) as a function of poly 1 gate voltage(V_(poly 1)) while keeping the select transistor 110 V_(p2) at justabove its threshold. In this way most of the potential drop in channel106 of FIG. 1 occurs in channel portion 106-1 underneath gate 109 ofselect transistor 110, and electrons accelerated in this channel arethen injected onto floating gate 107. From FIG. 3 it is seen the hotelectron programming injection efficiency of this device is phenomenallyhigh.

[0106] Various embodiments of a process suitable for fabricating astructure in accordance with the embodiment of FIGS. 1a-1 d are nowdescribed. Reference can also be made to copending U.S. application Ser.No. 323,779 filed Mar. 15, 1989 (now U.S. Pat. No. 5,070,032), andassigned to SunDisk, the assignee of this invention. Reference may alsobe made to fabrication process steps described earlier in thisapplication. A starting substrate is used, for example a P typesubstrate (or a P type well region within an N type substrate). A layerof oxide is formed, followed by a layer of silicon nitride. The layer ofsilicon nitride is then patterned in order to expose those areas inwhich N+ source and drain regions are to be formed. The N+ source anddrain regions are then formed, for example, by ion implantation ofarsenic to a concentration of approximately 1×10²⁰ cm⁻³. The wafer isthen oxidized in order to form oxide layers 104 and 105 in order tocause source and drain regions 102 and 103 to become “buried”. Note thatfor the embodiment of FIG. 2a, this oxidation step is not utilized, asthe source and drain regions are not “buried”. Rather, the source anddrain regions are formed after all polycrystalline silicon layers areformed, in a conventional manner. The remaining portion of the nitridemask is then removed, and the oxide overlying channel regions 106-1 and106-2 is removed. A new layer of gate oxide overlying channel regions106-1 and 106-2 is formed, for example to a thickness within the rangeof 150 Å to 300 Å and implanted to the desired threshold (e.g.approximately −1 v to +1 v). Polycrystalline silicon is then formed onthe wafer and patterned in order to form floating gate regions 107. Ifdesired, the polycrystalline silicon layer is patterned in horizontalstrips (per the orientation of FIG. 1a), with its horizontal extentpatterned at the same time as the patterning of the second layer ofpolycrystalline silicon, as will be now described. Following theformation polycrystalline silicon layer 107 at this time, a layer ofoxide or oxide/nitride dielectric is formed over the remaining portionsof polycrystalline silicon layer 107. A second layer of polycrystallinesilicon 108 is then formed and doped to a desired conductivity, forexample 30 ohms/square. The second layer of polycrystalline silicon isthen patterned into vertical strips (again, per the orientation of FIG.1a). If the horizontal extent of polycrystalline silicon layer 107 wasnot earlier defined, this pattern step is also used to remove the layerof dielectric between the first and second layers of polycrystallinesilicon in those areas where the first layer of polycrystalline siliconis to be patterned simultaneously with the patterning of the secondlayer of polycrystalline silicon. Following the first layer patterning,an additional layer of dielectric is formed on the wafer to form thegate dielectric above channel region 106-1, and above any other areas inthe silicon substrate to which the third layer of polycrystallinesilicon is to make a gate. These regions can then be implanted to thedesired threshold voltage (e.g. approximately 0.5 v to 1.5 v). The thirdlayer of polycrystalline silicon is for a transistor (ranging from 200 Åto 500 Å in thickness) then formed and doped to appropriateconductivity, for example 20 ohms/square. Polycrystalline silicon layer109 is then patterned in order to form word line 109.

[0107] In one embodiment of this invention, polycrystalline siliconlayer 107 is patterned to form horizontal stripes and channel stopdopants (e.g. boron) are implanted into the exposed areas therebetweenin order to form high threshold channel stop regions between adjacentrows of a memory array. The thickness of the gate dielectric betweenchannel 106-2 and polycrystalline silicon floating gate 107 can rangefrom approximately 150 angstroms or less to approximately 300 angstromsor more, depending on performance tradeoffs. For increased drive forreading, a thinner gate dielectric is desired while for increasedcoupling between polycrystalline and silicon control gate 108 andfloating gate 107 (helpful during programming) a thicker gate dielectricis desired.

Second Embodiment

[0108]FIG. 5 is a two-poly embodiment in which programming occurs bytaking drain 303 high, for example about 10V while raising control gate308 just sufficiently so as to turn on select transistor 310. Since thisV_(CG) voltage can vary from one device to another it is possible toachieve the optimum injection conditions by keeping V_(CG) at about 3Vwhile raising source (virtual ground) 302 in a sawtooth fashion fromabout 0 to 3 volts and back to 0 again, with a period on the orderapproximately 1 microsecond.

[0109] This ensures that at some point along the sawtooth the optimuminjection conditions are met. Reference can also be made to EuropeanPatent Application Serial No. 89312799.3 filed Aug. 12, 1989. To furtherenhance programming efficiency, in one embodiment a programmingefficiency implant 330 (shown in dotted line) is introduced at thesource side. To read the device, its source is 0V, drain isapproximately 1.0 v and V_(CG) approximately 4.5-5 v. To erase we employpoly 1-poly 2 tunneling between floating gate 307 in word line 308 atthe tunneling zone, consisting of one or more of the floating gateedges, sidewall, corners of the top edge, portions of the top andportions of the bottom, of floating gate 307, associated with a tunneloxide (400 Å-700 Å). Erase takes place with V_(CG) approximately 12-22V,V_(D)=0V, V_(S)=0V. A capacitive decoupling dielectric (approximately1500 to 2000 Å thick) 340 is formed on top of poly 1 to reduce thecapacitance between poly 1 and poly 2.

[0110] In one embodiment of this invention, a high electrical fieldregion is created in the channel far away from the reverse field regionlocated in conventional devices near the drain. This is achieved, forexample, by utilizing region 330 of increased doping concentration atthe boundary between channels 306-1 and 306-2 under floating gate 307.In one embodiment, the width of region 330 is on the order of 0.1microns. A larger dimension for region 330 can be counterproductive,reducing the select transistor drive with no gain in efficiency.

[0111]FIG. 4 depicts the electrical field distribution along channels306-1 and 306-2 in structures with and without P+ doped region 330. In astructure without region 330 and improperly biased select transistor theelectron injection can take place in the high field region near drain303. Because of the vertical field reversal region near drain 303, theresultant injection efficiency is reduced. In a structure with region330 the injection takes place in the high field region located at region330, far away from the field reversal region. Because of this, increasedinjection efficiency is achieved.

[0112] From the processing side there are three problems which must beaddressed properly:

[0113] 1. The formation of sufficiently thin/high quality gatedielectric over BN+, which tends to oxidize more quickly than undopedsilicon.

[0114] 2. The misalignment between poly 1 and the buried N+ draindiffusion strongly affects the coupling ratios for programming anderase. This can be overcome at the expense of an increase in cell areaby not using a virtual ground array, but instead a shared source array.

[0115] 3. This array permits floating gate 307 to completely overlap theburied N⁺ diffusion in a dedicated source arrangement, eliminating thisalignment sensitivity. Unfortunately, this array requires an extraisolation spacing adjacent to the BN+ to prevent the poly 1 extensionbeyond BN+ in the direction away from channel 306-2 to form a transistorin the neighboring cell.

[0116] To achieve small cell size in the buried diffusion direction achannel stop isolation is used between adjacent cells, plus aself-aligned stacked etch to simultaneously delineate poly 2 and poly 1.This is difficult to do without pitting the substrate as well as theexposed BN+ when etching the exposed poly 1 between adjacent cells. Thisis especially difficult to avoid when etching the decoupling oxide(1500-2000 Å thick on top of poly 1 in order to expose poly 1, since thesubstrate unprotected by poly 1 also becomes exposed, so that when poly1 is etched, the substrate in those regions becomes pitted.

[0117] This will therefore require formation of a thick dielectricregion as part of the field isolation process protecting the substratein the space between the poly 2 word lines. This can be accomplished byusing a process as described in U.S. patent application Ser. No.323,779, filed Mar. 15, 1989, and assigned to SunDisk, the assignee ofthis application. This is actually forming trench isolation, but withBN+ abutting this trench, we may experience severe junction leakage aswell as loss of a portion of the BN+ conductor. This cell of this secondembodiment is attractive because it is double poly, low programmingcurrent, very fast programming, programming away from drain junction,small and scalable cell. Cell size is quite attractive as indicatedbelow for three representative geometries:

1.0 m geometries:cell=4.0×2.0=8.0 m²

0.8 m geometries:cell=3.2×1.6=5.2 m²

0.6 m geometries:cell=2.3×1.2=2.8 m²

Third Embodiment

[0118]FIG. 6 is a cross-sectional view of alternative embodiment of atwo poly cell, using source side injection for programming, aided bystrong coupling to buried N+ drain 403, which acts also as a secondcontrol gate. Erase is by Fowler-Norheim tunneling to channel 406through a small thinned oxide region, formed for example to a thicknessof about 100 Å, by utilizing a thin polyspacer. These process stepswould be as follows: Once the drain oxide is formed (i.e. the oxideabove drain 403), a first layer of poly, (approximately 2000 Å to 4000 Åthick) is deposited and a thin nitride dielectric is deposited on top.These layers are then etched using a poly 1 mask to delineate thelateral extent (as shown in FIG. 6) of the poly 1. A second layer ofnitride is then deposited and anistropically etched back to underlyingoxide, leaving the initial nitride layer on top of poly 1 plus nitridespacers along the poly 1 sidewalls. This protects the poly 1 sidewallfrom subsequent oxidation, allowing electrical contact to be made aslater described. The exposed oxide layer over the channel portion of thesubstrate is then stripped and regrown to the 100 Å thickness requiredfor tunneling, while a photoresist masked pattern protects oxide overthe exposed, BN+ side of the poly 1 from being stripped. The nitridelayers surrounding poly 1 prevent oxide from forming on that poly. Thethin nitride is then etched off using a highly selective etch which doesnot attack or degrade the 100 Å tunnel oxide (e.g. hot phosphoric orplasma etch). This is followed by a second poly deposition whichelectrically contacts the first poly on its top surface and itssidewalls. This structure is then etched using an anisotropicpoly-silicon etch, with etch being terminated with the re-exposure ofthe oxide layers over substrate beneath the second deposited poly layer.This completes the formation of the poly 1 floating gate stripe shown inFIG. 6. The remaining process is similar to that of the secondembodiment.

[0119] In this embodiment, programming is from hot channel electronsinjected from grounded source diffusion 402 with drain 403 held at about+8 v and fixed control gate of around 1.5 v. Alternatively, programmingis performed by hot channel electrons from source diffusion 402utilizing a sawtooth control gate voltage ranging from 0 volts to a peakvoltage approximately 3 volts, as described previously for the secondembodiment. Read is achieved with V_(DS) =1.5V, Vs=0, V_(C)G=+5V. Eraseis achieved with V_(CG) =−22V, Vs=Vd=0V. In this embodiment, the poly 2word line 408 will carry the +5 volts during read and the −22 voltsduring erase, thereby requiring an X-decoder capable of serving thispurpose. Coupling considerations require that ^(C)P2P1 ²²CP1D, which isunfavorable for programming. Therefore the cell must be optimized forbalancing erase against programming by adjusting oxide thicknesses andfloating gate threshold to the optimum print. There is less of a problemwith pitting the field regions between cells in the poly 1 direction(because poly 1—poly 2 oxide or ONO is thin). This may obviate the needfor the additional thick oxide field region described for the secondembodiment. However, there is the additional process complexity offorming the thin oxide region and extra space needed to place this thinoxide region sufficiently far from the source diffusion.

Alternative Operating Methods

[0120] A number of alternative methods are possible to program thesource side injection cells described in the previous embodiments.Strong capacitive coupling (for example, using thin ONO) is required inthe second and third embodiments between poly 2 and drain, and betweenpoly 2 and poly 1, respectively, for programming. During operation, oneembodiment applies V_(D) at 5 to 7 v, V_(s)=0, the control gate voltageV_(CG) is raised to just turn on the control gate channel, and V_(p2) ison the order of about 12 volts or more. Alternatively, the source bodyeffect is used to advantage. In this alternative embodiment, rather thanbringing control gate to a specified value to just turn on the channel,the control gate is brought to a value greater than the voltage requiredto just turn on the channel (e.g., approximately one volt above) and apull-down circuit is used (e.g., a high impedance resistor or a currentsink) for providing approximately 1 μA current flow via sourcedebiasing. Alternatively, the control gate voltage V_(CG) can beoperated in a sawtooth fashion from between 0 volts to about +3 volts,as mentioned previously with respect to European patent applicationserial number 89312799.3.

Multi-bit Cells

[0121] In an alternative embodiment of this invention, such as is shownin FIGS. 9a and 9 b, a novel structure is taught including a multi-bitsplit gate cell, using source side injection programming and usingpoly-to-poly tunneling for erase. The following describes, in moredetail, the operation of one embodiment of such a structure of thisinvention.

[0122] Basic read operation for such a cell consists of applyingappropriate control gate bias (e.g. 8 v—see TABLE 4) to the unreadportion (henceforth for convenience to be termed the transfer portion),while applying the required read control gate bias to the portion beingsensed (in multi-state this would be a bias level appropriate to thestate being sensed for). In one embodiment, the select gate bias is heldat approximately 1.5 volts to keep total cell current limited (e.g. toabout 1 microamp), independent of the floating gate conduction level.Alternatively, the select gate bias is maintained at any desired level,e.g. about 5 volts, depending on the current sensing requirements.Similarly, to program a bypass applied on the transfer portion (about 12v) and a writing potential on the control gate portion (again inmulti-state this would be a bias level appropriate to the state beingwritten), with the select gate bias throttled for source side emission(about 1.5 v), and the drain bit line (the bit line adjacent theto-be-programmed floating gate) raised to about 5 v for programming,with the source bit line (adjacent to transfer portion) grounded. TABLE4 OPERATING MODES/CONDITIONS CONDITION BL2 BL1 CGL2 SG1 CGR2 READSTANDBY X X  0v X X READ UNSELECTED FLOAT X 1.5v X FLOAT READ FGL12  0vREAD 1.5v  8v 1.5v VREF READ FGR12 1.5v  8v 1.5v READ  0v VREF ERASE  0v 0v VE  0v  0v PROGRAM STANDBY X X 0v X X PROG UNSELECTED FLOAT X 1.5v XFLOAT PROG FGL12  5v PROG 1.5v 12v  0v VREF PROG FGR12  0v 12v 1.5v PROG 5v VREF

[0123] Following are some key advantages of the multi-bit cell of thisembodiment of this invention:

[0124] (1) Approaches (2*lambda)² cell size

[0125] (2) Highly self-aligned

[0126] (3) High efficiency source side programming, resulting in lowerpower and lower voltage requirements, allowing greater parallelismduring write

[0127] (4) Attractive for scalability

[0128] (5) Totally immune to overerase

[0129] This cell can achieve (2*lambda) cell size, where lambda is theminimum lithographic feature, because (1) each of its lateral componentparts, in both its word line and bit line directions, can be formedusing this minimum lambda feature, and (2) the various criticalcomponents are self-aligned to one another, obviating the need toincrease cell size to accommodate lithographic overlay registrationrequirements. For example, viewing along the row or word line direction,the floating gate poly2/1 self-aligned stacks and their underlyingchannels can be formed using the minimum feature lithographic width(lambda), while the transfer channels and bit line diffusions can besimultaneously delineated using the minimum lithographic space betweenfeatures (also lambda), giving it a (2*lambda) minimum pitch capabilityalong this direction. Similarly, looking along the poly2 steering gatein the bit line direction, the channel regions underlying poly1 floatinggate and poly3 word line can be formed using the minimum lithographicfeature (lambda), while the isolation region between word line channelscan be formed by the minimum lithographic space (also lambda), againachieving the minimum pitch of (2*lambda). In this way, the cellachieves the (2*lambda)² minimum layout area. It is in fact aself-aligned cross-point cell, the poly2/1 stack and correspondingchannel being fully self aligned to the transfer channel and bit linediffusions, and in the orthogonal direction the isolation beingself-aligned to the channel areas. When combining this with the lowvoltage requirement made possible by the source-side injectionprogramming mechanism, this makes it an ideal element for still furtherscaling (i.e. smaller lambda). Finally, its immunity to overerase comesfrom the following two factors: (1) the presence of the seriestransistor channel select region, which fully cuts off cell conductionwhen deselected, independent of degree of erasure, and (2) thesource-side injection mechanism itself, which is enhanced with strongovererase, in contrast to the more conventional drain-side programming,which becomes retarded by strong levels of erasure.

[0130] In one embodiment, rather than the use of 100 Å tunneling oxidefor the erase operation as in the prior art Ma approach, a thick oxide,geometrically enhanced, poly-to-poly tunneling approach is used, asshown for example in FIGS. 9a and 9 b, where the poly3 word line servesthe dual function of cell selection and erase anode (one of thearchitecture/operational approaches taught in the above-mentionedSunDisk U.S. Pat. No. 5,313,421). FIGS. 10a and 10 b shows theequivalent circuit of this cell/array and TABLE 4 summarizes itsoperation.

[0131] The advantages of this embodiment include:

[0132] Erase unit to follow row line(s), resulting in row orientedsectoring;

[0133] Avoids need to use negative voltages, erase being accomplished byholding all electrodes at ground, except for the selected sector(s)poly3 word lines, which are raised to erase potential (about or lessthan 20 v);

[0134] High reliability inherent to thick oxide tunnelingimplementation; and

[0135] Improved scalability inherent to the use of the thick interpolyoxide (and consequent reduced parasitic capacitance, both because of thegreater thickness and because of the small sidewall vicinity limitedtunneling area), combined with the high degree of vertical integration(vertically stacked poly3 word line serving the dual role of select gateand erase electrode).

[0136] Such a cell approach offers the potential for a physicallyminimal (4*lambda²), highly self aligned, crosspoint cell, which is bothvery reliable (use of thick oxides and no high voltage junctionrequirements within memory array), and readily scalable (via the sourceside injection element and its reduced voltage and more relaxed processcontrol requirements, combined with the inherent salability of thevertically integrated, thick oxide interpoly erase element). From aphysical point of view therefore, a Gigabit (or greater) density levelembodiment based on a 0.25μ technology, has a per bit area ofapproximately 0.25μ².

[0137] Despite the series nature of the dual gate cell, a four levelmulti-state (two logical bits per floating gate, or four logical bitsper dual gate cell) can be implemented. The key requirement is that themost heavily programmed state plus bias level of the transfer floatinggate's control gate be optimally selected to expose the full multi-stateconduction range of the memory floating portion, without introducingread disturb. Based on the above example, a four-level multi-stateimplementation would give a per bit area approaching 0.1μ²(approximately 0.125μ²).

[0138] In summary, the above described dual-gate cell based on the thickoxide, row oriented erase approach offers a novel, non-obviousimplementation, one that offers significant improvements over the priorart in scalability, reliability and performance.

Alternative Embodiment Utilizing Negative Steering Cell Operation

[0139] The control gate (or steering) bias voltage level or range oflevels for reading constitute a powerful parameter in setting the memorywindow voltage position and corresponding ranges for the steeringelement during programming operations and the poly3 control/eraseelement during erase. By allowing this level or range of levels to gobelow 0 v, this allows shifting up of the floating gate voltage memorywindow (due to its associated charge) by a proportional amount, governedby the steering gate coupling ratio. The net result is the maximumsteering gate voltage level, for both sensing and programming, isreduced by that negatively shifted amount. Similarly, with the steeringgate taken below 0 v during erase, the maximum erase voltage is alsolowered, the amount of which is proportional to the steering gatecoupling ratio.

[0140] An important parameter in determining steering voltage magnitudesis the steering gate coupling ratio, RCG (or R21)=C21/CTOT, where C21 isthe capacitance between the poly1 floating gate and the poly2 steeringgate, and CTOT is the total floating gate capacitance. For example, ifthe net requirement for read plus programming is to capacitively shiftthe floating gate potential by 10 v, then given an RCG of 50%, thesteering voltage swing must be scaled up by 1/RCG, giving a 20 v swing.If, on the other hand, RCG is increased to 66.7%, the steering voltageswing drops to 15 v, a savings of 5 v. Using this 66.7% value, if theread steering bias voltage level (or range) is lowered by 7.5 v, thepoly3 erase voltage is lowered by RCG*7.5 v, a savings of 5 v over thenon-lowered bias situation.

[0141] In order to implement negative steering into an N channel based,grounded substrate memory array, one embodiment utilizes P channelcircuitry, capable of going negative of ground, to generate anddistribute this bias. In order to support the full steering voltagedynamic range, the N well for such P channel circuitry is biased to themaximum required positive voltage, and the P channel circuitry can thusfeed any potential from that value on down to the most negative required(independent of memory array ground). The positive and negative voltagelimits are provided from either external supplies or readily generatedon chip (for example by N channel based charge pumps for positive biasand P channel for negative bias), since no DC current is required forsteering (only capacitive load charging).

[0142] In one embodiment, a full column oriented array segmentation isimplemented to form one sector or a group of row oriented sectors,wherein one sector is read or programmed at any given time. All cells inone sector are erased simultaneously, and one or more sectors can beselected for simultaneous erasure. Column based segmentation breaks afull array into a multiplicity of segmented sub-arrays, therebyeliminating large and/or cumulative parasitics such as capacitance andleakage. Each sub-array has its own set of local bit line diffusions andpoly2 steering lines, which are selectively connected by segment selecttransistor matrixes to corresponding global bit lines and steeringlines.

[0143]FIG. 10c exemplifies such a segmentation embodiment, depicting onesegment, denoted as SEGMENT I, consisting of N rows of cells (e.g. Nequalling 32). For example, each row forms one sector consisting of 2048dual gate cells or equivilantly 4096 floating gate storage elements.Alternatively, a sector can be formed by a group of two or more rows.The long, continuous, global bit lines (typically run in metal) BLk areselectively connected to the local segment subcolumns through theSegment Bit Line Transfer Select transistors 1001, 1002, driven by theSEGi lines. Similarly, the long, continuous global steering lines(typically run in metal) Sk are selectively connected to the localsegment steering gates through the Steering Drive Transfer Selecttransistors 2001, 2002, driven by the STD_ODDi and STD_EVENi lines. Inthis way array segments are isolated from one another, eliminating thelarge cumulative parasitics of leakage and capacitance, and providingcolumn associated defect and repetitive disturb confinement.

[0144] Performance can be increased by simultaneously operating on asmany cells in one row as possible (where a row may have anywhere from 1Kto 4K floating gate memory transistors), thereby maximizing parallelism.Peak power is not a limitation in such implementation, because of thelow cell operating currents inherent to this cell approach both duringread and programming operations. Consequently, the number of floatinggate transistors per row which can be simultaneously operated on islimited only by addressing constraints and segment decode restrictions.For the embodiment shown in FIG. 10c, this allows every 4th floatinggate to be addressed and operated on, simultaneously, as outlined inTABLE 5, allowing the full row to be addressed and operated on in fourpasses as follows.

[0145] During each pass, two adjacent diffusions are driven to drainpotential followed by two adjacent diffusions driven to ground, withthat bias pattern repeated across the entire row of cells. In this wayglobal drain/source bias is applied in mirrored fashion to every otherof the selected cells, resulting in floating gate bias conditions of oddselected cells being reversely applied to those of the even selectedcells. Appropriate biases are placed on the global steering lines, asexemplified in TABLE 5, to satisfy the operation of the targetedfloating gates as given in TABLE 4, while the local steering lines ofthe unselected cells are discharged and left isolated from the globalsteering lines. Once done, the bias conditions for both globalbit/ground lines and targeted/untargeted floating gate steering linesare correspondingly interchanged to operate on the other of the floatinggate pair within the selected cells. Once this is completed, similaroperation is repeated to the alternate set (i.e. previously unselectedset) of cells, thereby completing full row programming in four passes.TABLE 5 CELLS K − 3L K − 3R K − 2L K − 2R K − 1R K − 1L KR KL K + 1L K +1R K + 2L K + 2R GLOBAL BIT LINES K + 3R K + 3L K + 4R K + 4L BLK − 3BLK − 2 BLK − 1 BLK BLK + 1 BLK + 2 BLK + 3 BLK + 4 READ PASS 1 SELUNSEL UNSEL UNSEL 0 1.5 1.5 0 0 1.5 1.5 0 PASS 2 UNSEL SEL UNSEL UNSEL1.5 0 0 1.5 1.5 0 0 1.5 PASS 3 UNSEL UNSEL SEL UNSEL 0 0 1.5 1.5 0 0 1.51.5 PASS 4 UNSEL UNSEL UNSEL SEL 1.5 1.5 0 0 1.5 1.5 0 0 PROGRAM PASS 1SEL UNSEL UNSEL UNSEL 5 0 0 5 5 0 0 5 PASS 2 UNSEL SEL UNSEL UNSEL 0 5 50 0 5 5 0 PASS 3 UNSEL UNSEL SEL UNSEL 5 5 0 0 5 5 0 0 PASS 4 UNSELUNSEL UNSEL SEL 0 0 5 5 0 0 5 5 ERASE SEL SEL SEL SEL 0 0 0 0 0 0 0 0CELLS K − 3L K − 3R K − 2L K − 2R K − 1R K − 1L KR KL K + 1L K + 1R K +2L K + 2R GLOBAL STEERING LINES K + 3R K + 3L K + 4R K + 4L SK − 3 SK −2 SK − 1 SK SK + 1 SK + 2 SK = 3 SK + 4 READ PASS 1 SEL UNSEL UNSELUNSEL VREFR  8  8 VREFR VREFR  8  8 VREFR PASS 2 UNSEL SEL UNSEL UNSEL 8 VREFR VREFR  8  8 VREFR VREFR  8 PASS 3 UNSEL UNSEL SEL UNSEL VREFRVREFR 8 8 VREFR VREFR 8 8 PASS 4 UNSEL UNSEL UNSEL SEL  8  8 VREFR VREFR 8  8 VREFR VREFR PROGRAM PASS 1 SEL UNSEL UNSEL UNSEL VREFP 12 12 VREFPVREFP 12 12 VREFP PASS 2 UNSEL SEL UNSEL UNSEL 12 VREFP VREFP 12 12VREFP VREFP 12 PASS 3 UNSEL UNSEL SEL UNSEL VREFP VREFP 12 12 VREFPVREFP 12 12 PASS 4 UNSEL UNSEL UNSEL SEL 12 12 VREFP VREFP 12 12 VREFPVREFP ERASE SEL SEL SEL SEL  0  0  0  0  0  0  0 0 CELLS K − 3L K − 3R K− 2L K − 2R ROW LINES K − 1R K − 1L KR KL SEGMENT _I LINES SELECTED K +1L K + 1R K + 2L K + 2R STD STD ROW _J UNSELECTED K + 3R K + 3L K + 4RK + 4L EVEN_I ODD_I SEG_I LINE ROW READ PASS 1 SEL UNSEL UNSEL UNSEL 010 5 1.5 0 PASS 2 UNSEL SEL UNSEL UNSEL 0 10 5 1.5 0 PASS 3 UNSEL UNSELSEL UNSEL 10 0 5 1.5 0 PASS 4 UNSEL UNSEL UNSEL SEL 10 0 5 1.5 0 PROGRAMPASS 1 SEL UNSEL UNSEL UNSEL 0 14 8 1.5 0 PASS 2 UNSEL SEL UNSEL UNSEL 014 8 1.5 0 PASS 3 UNSEL UNSEL SEL UNSEL 14 0 8 1.5 0 PASS 4 UNSEL UNSELUNSEL SEL 14 0 8 1.5 0 ERASE SEL SEL SEL SEL 5 5 5 <20 0

[0146] To give an idea of the high speed of this approach with respectto programming, assuming a physical row of 4096 floating gate elements,and 10 μsec per pass for cell programming, this gives an effectiveprogramming time of ˜10 nsec/bit or a raw programming rate of 4096 bitsper 40 μsec (i.e. per 4*10 μsec) or ˜12.5 MBytes/sec.

[0147] In order to accommodate the negatively shifted steering in thisembodiment, the steering segmentation transistor matrix is implementedin positively biased N well, P channel based circuitry.

[0148] As indicated above, in order to reduce maximum voltage levelsrequired, it is desirable to keep the steering gate coupling ratiorelatively high, for example, greater than approximately 60%, (see FIG.10a for one embodiment of a cell equivalent circuit). In one embodiment,ONO interpoly2/1 dielectric (with, for example, an effective tox of 200Å) is used, combined with a cell structure and process approach(described below), which reduces the parasitic substrate andinterpoly3/1 capacitances.

[0149] Parasitic capacitances to substrate and drain are, in oneembodiment, kept small by using a narrow channel structure, bounded bymuch thicker field oxide regions (such isolation structure is describedin U.S. Pat. No. 5,343,063). By way of example, a cell with a narrow(for example, about 0.1μ wide), approximately 300 Å thick gate oxidechannel region bounded by about 1500 Å thick field regions, whosefloating gates are laid out so as to substantially overlap those thickfield regions (for example with a total overlap of about 0.3μ), would,in combination with the scaled ONO interpoly2/1, provide steeringcapacitance magnitudes of around five times larger than those of thefloating gate to substrate/drain.

[0150] In order to reduce the interpoly3/1 capacitance, it must first benoted that in this dual floating gate Flash cell, poly3 crosses twoedges of the poly1 floating gate, resulting in approximately double theinterpoly3/1 capacitance of cells in which poly3 crosses only a singlepoly1 edge (for which parasitic coupling ratios are typically around15%). Although the double edge structure may offer benefits to the erasetunneling element (e.g. voltage levels and distributions), its benefitis outweighed by the higher erasing and programming gate voltages neededto offset the associated poorer coupling efficiencies. Therefore, it isdesirable to eliminate the capacitive impact of one of these two edges,even if in doing so its erase tunneling contribution is also eliminated.The following discussion describes one embodiment of a process toaccomplish this, integrated into the self-aligned diffusion (BN+)formation process.

[0151] To realize a self-aligned BN+ cell, the BN+ sources/drains mustbe formed after the poly2/1 stack etch (i.e. self-aligned to poly2 )thereby realizing the physically smallest cell. The challenge here is toremove the field oxide locally over the S/D region to allow BN+ Asimplant, while at the same time preserving sufficiently thickdielectrics surrounding the poly2 steering line for poly3 to poly2 highvoltage isolation. The following section details the above mentionedexemplary process.

[0152] In looking at the twin cell in cross-section (see FIGS. 11a-11 efor top view and various cross-sections, and in particular FIG. 11e),the process strategy to achieve both self-aligned BN+ formation andpoly3/1 coupling reduction lies in the ability to separately process thetwo distinct regions, namely (1) the vertical strip regions associatedwith the BN+ and (2) the vertical strip containing the select channelportions. In so doing, the poly3/1 tunneling edge can be restricted toonly form adjacent to the select strip, while completely eliminating itsformation along the poly1 edge bordering the BN+ strip.

[0153] This is accomplished in the following manner (refer to FIG. 12afor cross-sections in row line direction, following some of the keyprocess steps. NOTE: the poly3 row lines are defined here to runhorizontally, and the BN+ columns to run vertically) By way of example,the following discussion includes representative numbers for dimensionsand thicknesses, assuming a 0.25μ technology (printing minimumlithographic feature size, both width and space, to achieve minimumpitch).

[0154] Form field oxide 1100 to a thickness of about 1500 Å, and etch itinto horizontal strips, adding appropriate channel/field implants priorto or at this step. Use an oxide spacer approach to reduce channel width(for example, reduce from about 0.25μ as etched to about 0.1μ postspacer formation, thereby improving control gate coupling). Growfloating gate oxide 1101, (approximately 300 Å gate oxide). As shown inSundisk U.S. Pat. No. 5,343,063 the fabrication steps up through theforming of poly1 1102 to a thickness of about 1500 Å are performed.Poly1 is then etched into horizontal strips overlying the channelregions plus generous overlap on the field region to either side of thechannel. As with channel width, a spacer approach can be used todecrease the etched poly1 spacing, thereby increasing net poly1 overlapof field oxide, or “wings”. For example, after the spacer step, poly1spacing is reduced to about 0.1μ, giving poly1 wings of about 0.15μ perside—refer to FIG. 11b showing a cross-section through the channel alongthe column direction for an example of poly1 wings over field oxide.Note that because of the narrow channel widths vis a vis the poly1thickness, poly1 1102 will completely fill the trench, resulting in asubstantially planar surface. Next form thin ONO 1103 (for example,having about 200 Å tox effective) on top of and along edges of the poly1strips. In an alternative embodiment, a portion of the top film isformed as part of an initially deposited poly1 layer stack.

[0155] Referring to FIGS. 12a(i) and 12 a(ii), deposit a sandwich layerof poly2 1104 (about 1500 Å), thick poly3/2 isolation oxide 1105(approximately 2000 Å), plus a sufficiently thick etch stopping layer1106 (to block underlying oxide removal when exposed to oxide typeetch), and top oxide layer 1107. Using a patterned photoresist maskinglayer 1108, these are then etched in strips along the column direction,down to the poly1 layer, to form poly2 the steering gate lines. Theseexposed poly1 regions are overlying the areas to become select channeland BN+.

[0156] Referring to FIGS. 12b(i) and 12 b(ii), strip previousphotoresist and pattern new photoresist layer 1109 to cover and protectexposed poly1 over the select channel regions. Etch exposed poly1 1102and all its underlying oxide 1101 which cover the to-be-formed BN+regions. Oxide layer 1107 over etch stopping layer 1106 is used toprotect etch stopping layer 1106 from being etched by the poly etch aspoly1 1102 is being removed. Etch stopping layer 1106 (e.g. thin undopedpolysilicon or possibly nitride—must have low etch rate compared tooxide etch rates) is used to prevent that portion of thick poly3/2isolation oxide 1105 not covered by photoresist 1109 from being etcheddown as oxide 1101 beneath poly1 1102 is etched away. The oxide etchsystem used is both highly anisotropic (e.g. RIE) and selective vis avis the underlying silicon substrate, resulting in negligible etching ofthat substrate, accommodating the large differences in oxide thicknessesbeing removed between field oxide (approximately 1500 Å) and gate oxideregions (approximately 300 Å). Following completion of all etching,photoresist 1109 is removed.

[0157] Referring to FIGS. 12c(i) and 12 c(ii), at this point, an optionis to implant and drive a sufficient Boron dose to form a p+ DMOS typedoping profile adjacent to the BN+ junction (alternatively, this is thepoint at which the arsenic BN+ is implanted, but the resulting lateraldiffusion makes the floating gate channel unnecessarily short). As shownin FIGS. 12c(i) and 12 c(ii), oxide is formed and reactive ion etchedback down to silicon to form sidewall spacers 1110 (about 750 Å thick,with the thickness here being determined by interpoly3/2 erase highvoltage isolation requirements, for example, about 25 v) The arsenic BN+strips are then implanted.

[0158] Referring to FIGS. 12d(i) and 12 d(ii), a new patternedphotoresist layer 1111 is added to cover and protect BN+ strips. Theexposed poly1 over channel strips is etched, to expose the selectedchannel regions. (Since some of the poly1 overlies channel regions andis therefore thicker, while other portions overlie field oxide and isthinner, the same considerations for oxide etch selectivity apply asabove, in the oxide over BN+etching case.)

[0159] Referring to FIGS. 12e(i) and 12 e(ii), once photoresist 1111 isstripped, oxide is formed (e.g. via thermal oxidation or some compositeoxide) to simultaneously form the poly1 sidewall 1112 and cornerinterpoly3/1 tunneling oxides 1113 (for example, about 350 Å), the poly3gate oxide 1114 over the select channel and oxide 1115 over BN+ (e.g.less than about 300 Å—the requirement for both of these oxides beingthey must be sufficiently thick to reliably hold up to the erase voltageto substrate differential). A select transistor threshold adjust implantcan be optionally introduced at this time (e.g. increasing channeldopant concentration to raise select Vt, or introducing compensationimplant to reduce select Vt).

[0160] Referring to FIGS. 12f(i) and 12 f(ii), after deposition andpatterning of poly3 (which in one embodiment is polysilicide in order toreduce word line delay) the basic dual gate cell structure is complete.In one embodiment of this invention, a high electrical field region isenhanced in the channel far away from the reverse field region locatedin conventional devices near the drain and source regions. This isachieved, for example, by utilizing regions 1200 of increased dopingconcentration at the boundary between the channels 1201 and 1202 andtransfer channel region 1203. In one embodiment, the width of region1200 is on the order of 0.1 microns.

[0161] Using the above dimension and film thickness example values, thetotal floating gate capacitance becomes about 0.4 femptoFarads, andcoupling ratios are approximately: Steering Gate (R21) 70%; Erase Gate20%; Floating gate to Substrate & Drain 10%. Although this R21 value mayvary from this FIG. somewhat in that fringing fields from the otherterminals are not accounted for, this approximation indicates adequatecoupling ratios are achieved in the dual gate cell, even underaggressive cell scaling.

[0162] A process variant of the above approach, which can reduce furtherstill the erase coupling, is to completely fill the region over BN+ withan oxide, after BN+ formation. This is done, for example, by depositinga sufficiently thick, undensified (and hence easily etched away comparedto underlying densified oxide films) oxide layer, patterning photoresiststrips over the BN+ to protect it from etching, and etching away theexposed, undensified film over the select channel strips. Following thisstep and resist removal, the poly3/1 tunnel oxide process proceeds asoutlined above, during which time the oxide filler over BN+ isdensified.

[0163] The above approach and its variant outlines one of a number ofpossible ways to implement the above described dual floating gate cellinto the desired array.

[0164] In summary, several concepts have been introduced to implementingthe TWIN FG cell.

[0165] Fundamental to the cell is its low power source side programmingmechanism, and low power row oriented poly-to-poly erase element.Additionally, its independent steering and selection functions,facilitates low power, multi-state read and programming operations.

[0166] ONO interpoly2/1 is readily integrated to provide a highcapacitive coupling, ultra-low leakage steering element. One embodimentuses a full column segment confinement architecture to substantiallyreduce parasitic bit line capacitance and leakage.

[0167] A negatively shifted voltage steering implementation allowsreduction of maximum voltage ceilings for both the poly2 steering linesduring programming and the poly3 word/erase lines during erase. Undersuch implementation, one preferred embodiment for the column segmentedarray architecture is via an N-well isolated P channel steeringselection matrix.

[0168] High steering ratio is achieved by the narrow channel plus fieldoxide approach to allow formation of wings. A preferred embodiment isdescribed which reduces the interpoly3/1 parasitic as part of aself-aligned BN+ formation process. This replaces the thinner tunnelingoxide adjacent one of the two potential tunneling edges with a muchthicker isolation oxide. Based on the example used, this approach cangive a cell with steering coupling ratio approaching 70%, and parasiticerase coupling down to 20%. Furthermore, based on that example, whichuses a 0.25μ technology for the 4*lambda² dual floating gate, poly3word/erase line cell (where lambda is the minimum technology featuresize), a physical cell area of 0.25μ² is realizable, which for 8 (16)level of multi-state translates to an effective cell size approaching⁻0.08μ² (⁻0.06μ²) per logical bit. These small sizes, around 100 timessmaller than physical sizes of cells used in the 4MEG and 8MEGgeneration of Flash memories, are suitable for building Gigabit densitylevel Flash memories with comparable die sizes and at comparable costper die.

[0169] All publications and patent applications mentioned in thisspecification are herein incorporated by reference to the same extent asif each individual publication or patent application was specificallyand individually indicated to be incorporated by reference.

[0170] The invention now being fully described, it will be apparent toone of ordinary skill in the art that many changes and modifications canbe made thereto without departing from the spirit or scope of theappended claims.

What is claimed is:
 1. A memory structure comprising: a source region ofa first conductivity type; a drain region of said first conductivitytype; a first channel region of a second conductivity type opposite saidfirst conductivity type, located adjacent said source region; a secondchannel region of said second conductivity type opposite said firstconductivity type, located adjacent said drain region; a transferchannel region of said second conductivity type, located between saidfirst and second channel regions; a first floating gate located abovesaid first channel region; a second floating gate located above saidsecond channel region; a first control gate located above said firstfloating gate, serving as a steering element associated with said firstfloating gate; a second control gate located above said second floatinggate, serving as a steering element associated with said second floatinggate; a third control gate located above said transfer channel region,serving as a control gate of an access transistor, said third controlgate also overlying at least a portion of said first and second controlgates; a first tunneling zone formed between said first floating gateand said third control gate, and including one or more of edges, sidewall, corners of the top edge, portions of the top, and portions of thebottom of said first floating gate; and a second tunneling zone formedbetween said second floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 2. A memory structure comprising: a source region of a firstconductivity type; a drain region of said first conductivity type; afirst channel region of a second conductivity type opposite said firstconductivity type, located adjacent said source region, a portion ofsaid first channel region adjacent said source region being doped tosaid second conductivity type to a dopant concentration greater thanthat of said first channel region; a second channel region of saidsecond conductivity type opposite said first conductivity type, locatedadjacent said drain region, a portion of said second channel regionadjacent said drain region being doped to said second conductivity typeto a dopant concentration greater than that of said second channelregion; a transfer channel region of said second conductivity type,located between said first and second channel regions; a first floatinggate located above said first channel region; a second floating gatelocated above said second channel region; a first control gate locatedabove said first floating gate, serving as a steering element associatedwith said first floating gate; a second control gate located above saidsecond floating gate, serving as a steering element associated with saidsecond floating gate; a third control gate located above said transferchannel region, serving as a control gate of an access transistor; afirst tunneling zone formed between said first floating gate and saidthird control gate, and including one or more of edges, side wall,corners of the top edge, portions of the top, and portions of the bottomof said first floating gate; and a second tunneling zone formed betweensaid second floating gate and said third control gate, and including oneor more of edges, side wall, corners of the top edge, portions of thetop, and portions of the bottom of said second floating gate.
 3. Amemory structure comprising: a source region of a first conductivitytype; a drain region of said first conductivity type; a first channelregion of a second conductivity type opposite said first conductivitytype, located adjacent said source region; a second channel region ofsaid second conductivity type opposite said first conductivity type,located adjacent said drain region; a transfer channel region of saidsecond conductivity type, located between said first and second channelregions; a first floating gate located above said first channel region;a second floating gate located above said second channel region; a firstcontrol gate located above said first floating gate, serving as asteering element associated with said first floating gate; a secondcontrol gate located above said second floating gate, serving as asteering element associated with said second floating gate; a thirdcontrol gate located above said transfer channel region, serving as acontrol gate of an access transistor; a first tunneling zone formedbetween said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate; a second tunneling zone formed between said second floating gateand said third control gate, and including one or more of edges, sidewall, corners of the top edge, portions of the top, and portions of thebottom of said second floating gate; a first doped region at theinterface of said first channel region and said transfer channel region,said first doped region being doped to said second conductivity type andhaving a greater dopant concentration than that of said first channelregion and said transfer channel region; and a second doped region atthe interface of said second channel region and said transfer channelregion, said second doped region being doped to said second conductivitytype and having a greater dopant concentration than that of said secondchannel region and said transfer channel region.
 4. A memory arrayhaving a plurality of memory cells, comprising: a plurality of diffusedlines running in a first direction, serving as source and drain regionsof said memory cells, each memory cell having a first channel regionlocated adjacent said source region and a second channel region locatedadjacent said drain region, and a transfer channel region locatedbetween its said first and second channel regions; a plurality of firstfloating gates, each located above said first channel region of anassociated one of said memory cells; a plurality of second floatinggates, each located above said second channel region of an associatedone of said memory cells; a plurality of first control gate lines,running in said first direction, each located above an associated set ofsaid first floating gates and serving as steering elements associatedwith each said first floating gate; a plurality of second control gatelines, running in said first direction, each located above an associatedset of said second floating gates and serving as steering elementsassociated with each said second floating gate; and a plurality of rowlines, running in a second direction generally perpendicular to saidfirst direction, forming a set of third control gates above saidtransfer channel regions of each memory cell, overlying at least aportion of associated ones of said first and second control gates andserving as control gates of access transistors of associated memorycells, wherein each of said memory cells is associated with theintersection of one of said diffused lines and one of said row lines,and wherein each memory cell includes a first tunnelling zone formedbetween said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zoneformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 5. A memory array having a plurality of memory cells, comprising:a plurality of diffused lines running in a first direction, serving assource and drain regions of said memory cells, each memory cell having afirst channel region located adjacent said source region, a portion ofsaid first channel region adjacent said source region being doped tosaid second conductivity type to a dopant concentration greater thanthat of said first channel region and a second channel region locatedadjacent said drain region, a portion of said second channel regionadjacent said drain region being doped to said second conductivity typeto a dopant concentration greater than that of said second channelregion, and a transfer channel region located between its said first andsecond channel regions; a plurality of first floating gates, eachlocated above said first channel region of an associated one of saidmemory cells; a plurality of second floating gates, each located abovesaid second channel region of an associated one of said memory cells; aplurality of first control gate lines, running in said first direction,each located above an associated set of said first floating gates andserving as steering elements associated with each said first floatinggate; a plurality of second control gate lines, running in said firstdirection, each located above an associated set of said second floatinggates and serving as steering elements associated with each said secondfloating gate; and a plurality of row lines, running in a seconddirection generally perpendicular to said first direction, forming a setof third control gates above said transfer channel regions of eachmemory cell, and serving as control gates of access transistors ofassociated memory cells, wherein each of said memory cells is associatedwith the intersection of one of said diffused lines and one of said rowlines, and wherein each memory cell includes a first tunnelling zoneformed between said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zonesformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 6. A memory array having a plurality of memory cells, comprising:a plurality of diffused lines running in a first direction, serving assource and drain regions of said memory cells, each memory cell having afirst channel region located adjacent said source region and a secondchannel region located adjacent said drain region, and a transferchannel region located between its said first and second channelregions; a first doped region at the interface of each said firstchannel region and said transfer channel region, said first doped regionbeing doped to said second conductivity type and having a greater dopantconcentration than that of said first channel region and said transferchannel region; a second doped region at the interface of each saidsecond channel region and said transfer channel region, said seconddoped region being doped to said second conductivity type and having agreater dopant concentration than that of said second channel region andsaid transfer channel region a plurality of first floating gates, eachlocated above said first channel region of an associated one of saidmemory cells; a plurality of second floating gates, each located abovesaid second channel region of an associated one of said memory cells; aplurality of first control gate lines, running in said first direction,each located above an associated set of said first floating gates andserving as steering elements associated with each said first floatinggate; a plurality of second control gate lines, running in said firstdirection, each located above an associated set of said second floatinggates and serving as steering elements associated with each said secondfloating gate; and a plurality of row lines, running in a seconddirection generally perpendicular to said first direction, forming a setof third control gates above said transfer channel regions of eachmemory cell, and serving as control gates of access transistors ofassociated memory cells, wherein each of said memory cells is associatedwith the intersection of one of said diffused lines and one of said rowlines, and wherein each memory cell includes a first tunnelling zoneformed between said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zoneformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 7. A memory structure as in claims 1, 2, 3, 4, 5, or 6 whereinsaid first conductivity type is N and said second conductivity type isP.
 8. A memory structure as in claim 7 wherein said second conductivitytype is provided by boron dopants.
 9. A memory structure as in claims 1,2, 3, 4, 5, or 6 wherein said floating gates comprise a first layer ofpolycrystalline silicon, said first control gates comprise a secondlayer of polycrystalline silicon, and said third control gate comprisesa third layer of polycrystalline silicon.
 10. A memory structure as inclaims 1, 2, 3, 4, 5, or 6 which is capable of storing two or morelogical states.
 11. A memory array as in claim 10 wherein said floatinggates establish one of a plurality of predetermined charge levels forstoring a plurality of two or more logical states.
 12. A memorystructure as in claims 1, 2, 3, 4, 5, or 6 wherein said source regionand said drain region comprise buried diffusions.
 13. A memory structureas in claim 12 which further comprises a relatively thick dielectriclayer overlying said buried diffusions.
 14. A memory structure as inclaims 1, 2, 3, 4, 5, or 6 wherein said transfer channel is doped tosaid second conductivity type to a doped concentration greater than thatof first and second channel regions.
 15. A memory structure as in claims1, 2, 3, 4, 5, or 6 wherein said transfer channel is counter doped tosaid second conductivity type to a net doped concentration less thanthat of first and second channel regions.
 16. A memory array as inclaims 4, 5, or 6 organized into a plurality of sectors, each sectorcomprising one or more rows and organized such that erasure of all cellsof a sector is performed simultaneously.
 17. A memory array as in claims4, 5, or 6 organized as a virtual ground array.
 18. A memory array as inclaims 4, 5, or 6 wherein said one of first or second floating gates inalternate cells in a given row are verified simultaneously.
 19. A memoryarray as in claim 18 wherein an entire row is verified utilizing fourverification operations.
 20. A memory array as in claims 4, 5, or 6wherein said one of first or second floating gates of alternate cells ina given row are programmed simultaneously by placing data associatedwith each memory cell to be programmed on its associated diffused lines.21. A memory array as in claim 20 wherein an entire row is programmedutilizing four program operations.
 22. A method for forming a memorystructure comprising the steps of: forming a source region of a firstconductivity type; forming a drain region of said first conductivitytype; forming a first channel region of a second conductivity typeopposite said first conductivity type, adjacent said source region;forming a second channel region of said second conductivity type,adjacent said drain region; forming a transfer channel region of saidsecond conductivity type, between said first and second channel regions;forming a first floating gate above said first channel region; forming asecond floating gate above said second channel region; forming a firstcontrol gate above said first floating gate, serving as a steeringelement associated with said first floating gate; forming a secondcontrol gate above said second floating gate, serving as a steeringelement associated with said second floating gate; forming a thirdcontrol gate above said transfer channel region, serving as a controlgate of an access transistor, said third control gate also overlying atleast a portion of said first and second control gates; forming a firsttunneling zone between said first floating gate and said third controlgate, and including one or more of edges, side wall, corners of the topedge, portions of the top, and portions of the bottom of said firstfloating gate; and forming a second tunneling zone between said secondfloating gate and said third control gate, and including one or more ofedges, side wall, corners of the top edge, portions of the top, andportions of the bottom of said second floating gate.
 23. A method forforming a memory structure comprising the steps of: forming a sourceregion of a first conductivity type; forming a drain region of saidfirst conductivity type; forming a first channel region of a secondconductivity type opposite said first conductivity type, adjacent saidsource region, a portion of said first channel region adjacent saidsource region being doped to said second conductivity type to a dopantconcentration greater than that of said first channel region; forming asecond channel region of said second conductivity type, adjacent saiddrain region, a portion of said second channel region adjacent saiddrain region being doped to said second conductivity type to a dopantconcentration greater than that of said second channel region; forming atransfer channel region of said second conductivity type, between saidfirst and second channel regions; forming a first floating gate abovesaid first channel region; forming a second floating gate above saidsecond channel region; forming a first control gate above said firstfloating gate, serving as a steering element associated with said firstfloating gate; forming a second control gate above said second floatinggate, serving as a steering element associated with said second floatinggate; forming a third control gate above said transfer channel region,serving as a control gate of an access transistor; forming a firsttunneling zone between said first floating gate and said third controlgate, and including one or more of edges, side wall, corners of the topedge, portions of the top, and portions of the bottom of said firstfloating gate; and forming a second tunneling zone between said secondfloating gate and said third control gate, and including one or more ofedges, side wall, corners of the top edge, portions of the top, andportions of the bottom of said second floating gate.
 24. A method forforming a memory structure comprising the steps of: forming a sourceregion of a first conductivity type; forming a drain region of saidfirst conductivity type; forming a first channel region of a secondconductivity type opposite said first conductivity type, adjacent saidsource region; forming a second channel region of said secondconductivity type, adjacent said drain region; forming a transferchannel region of said second conductivity type, between said first andsecond channel regions; forming a first floating gate above said firstchannel region; forming a second floating gate above said second channelregion; forming a first control gate above said first floating gate,serving as a steering element associated with said first floating gate;forming a second control gate above said second floating gate, servingas a steering element associated with said second floating gate; forminga third control gate above said transfer channel region, serving as acontrol gate of an access transistor; forming a first tunneling zonebetween said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate; a second tunneling zone between said second floating gate and saidthird control gate, and including one or more of edges, side wall,corners of the top edge, portions of the top, and portions of the bottomof said second floating gate; forming a first doped region at theinterface of said first channel region and said transfer channel region,said first doped region being doped to said second conductivity type andhaving a greater dopant concentration than that of said first channelregion and said transfer channel region; and forming a second dopedregion at the interface of said second channel region and said transferchannel region, said second doped region being doped to said secondconductivity type and having a greater dopant concentration than that ofsaid second channel region and said transfer channel region.
 25. Amethod for forming a memory array having a plurality of memory cells,comprising the steps of: forming a plurality of diffused lines runningin a first direction, serving as source and drain regions of said memorycells, each memory cell having a first channel region located adjacentsaid source region and a second channel region located adjacent saiddrain region, and a transfer channel region located between its saidfirst and second channel regions; forming a plurality of first floatinggates, each located above said first channel region of an associated oneof said memory cells; forming a plurality of second floating gates, eachlocated above said second channel region of an associated one of saidmemory cells; forming a plurality of first control gate lines, runningin said first direction, each located above an associated set of saidfirst floating gates and serving as steering elements associated witheach said first floating gate; forming a plurality of second controlgate lines, running in said first direction, each located above anassociated set of said second floating gates and serving as steeringelements associated with each said second floating gate; and forming aplurality of row lines, running in a second direction generallyperpendicular to said first direction, forming a set of third controlgates above said transfer channel regions of each memory cell, overlyingat least a portion of associated ones of said first and second controlgates and serving as control gates of access transistors of associatedmemory cells, wherein each of said memory cells is associated with theintersection of one of said diffused lines and one of said row lines,and wherein each memory cell includes a first tunnelling zone formedbetween said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zoneformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 26. A method of forming a memory array having a plurality ofmemory cells, comprising the steps of: forming a plurality of diffusedlines running in a first direction, serving as source and drain regionsof said memory cells, each memory cell having a first channel regionlocated adjacent said source region, a portion of said first channelregion adjacent said source region being doped to said secondconductivity type to a dopant concentration greater than that of saidfirst channel region and a second channel region located adjacent saiddrain region, a portion of said second channel region adjacent saiddrain region being doped to said second conductivity type to a dopantconcentration greater than that of said second channel region, and atransfer channel region located between its said first and secondchannel regions; forming a plurality of first floating gates, eachlocated above said first channel region of an associated one of saidmemory cells; forming a plurality of second floating gates, each locatedabove said second channel region of an associated one of said memorycells; forming a plurality of first control gate lines, running in saidfirst direction, each located above an associated set of said firstfloating gates and serving as steering elements associated with eachsaid first floating gate; forming a plurality of second control gatelines, running in said first direction, each located above an associatedset of said second floating gates and serving as steering elementsassociated with each said second floating gate; and forming a pluralityof row lines, running in a second direction generally perpendicular tosaid first direction, forming a set of third control gates above saidtransfer channel regions of each memory cell, and serving as controlgates of access transistors of associated memory cells, wherein each ofsaid memory cells is associated with the intersection of one of saiddiffused lines and one of said row lines, and wherein each memory cellincludes a first tunnelling zone formed between said first floating gateand said third control gate, and including one or more of edges, sidewall, corners of the top edge, portions of the top, and portions of thebottom of said first floating gate, and wherein each memory cellincludes a second tunnelling zone formed between said second floatinggate and said third control gate, and including one or more of edges,side wall, corners of the top edge, portions of the top, and portions ofthe bottom of said second floating gate.
 27. A method of forming amemory array having a plurality of memory cells, comprising the stepsof: forming a plurality of diffused lines running in a first direction,serving as source and drain regions of said memory cells, each memorycell having a first channel region located adjacent said source regionand a second channel region located adjacent said drain region, and atransfer channel region located between its said first and secondchannel regions; forming a first doped region at the interface of eachsaid first channel region and said transfer channel region, said firstdoped region being doped to said second conductivity type and having agreater dopant concentration than that of said first channel region andsaid transfer channel region; forming a second doped region at theinterface of each said second channel region and said transfer channelregion, said second doped region being doped to said second conductivitytype and having a greater dopant concentration than that of said secondchannel region and said transfer channel region; forming a plurality offirst floating gates, each located above said first channel region of anassociated one of said memory cells; forming a plurality of secondfloating gates, each located above said second channel region of anassociated one of said memory cells; forming a plurality of firstcontrol gate lines, running in said first direction, each located abovean associated set of said first floating gates and serving as steeringelements associated with each said first floating gate; forming aplurality of second control gate lines, running in said first direction,each located above an associated set of said second floating gates andserving as steering elements associated with each said second floatinggate; and forming a plurality of row lines, running in a seconddirection generally perpendicular to said first direction, forming a setof third control gates above said transfer channel regions of eachmemory cell, and serving as control gates of access transistors ofassociated memory cells, wherein each of said memory cells is associatedwith the intersection of one of said diffused lines and one of said rowlines, and wherein each memory cell includes a first tunnelling zoneformed between said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zoneformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 28. A method as in claims 22, 23, 24, 25, 26, or 27 wherein saidfirst conductivity type is N and said second conductivity type is P. 29.A method as in claim 28 wherein said second conductivity type isprovided by boron dopants.
 30. A method as in claims 22, 23, 24, 25, 26,or 27 wherein said floating gates comprise a first layer ofpolycrystalline silicon, said first control gates comprise a secondlayer of polycrystalline silicon, and said third control gate comprisesa third layer of polycrystalline silicon.
 31. A method as in claims 22,23, 24, 25, 26, or 27 which is capable of storing two or more logicalstates.
 32. A method as in claim 31 wherein said floating gatesestablish one of a plurality of predetermined charge levels for storinga plurality of two or more logical states.
 33. A method as in claims 22,23, 24, 25, 26, or 27 wherein said source region and said drain regioncomprise buried diffusions.
 34. A method as in claim 33 which furthercomprises the step of forming a relatively thick dielectric layeroverlying said buried diffusions.
 35. A method as in claims 22, 23, 24,25, 26, or 27 wherein said transfer channel is doped to said secondconductivity type to a doped concentration greater than that of firstand second channel regions.
 36. A method as in claims 22, 23, 24, 25,26, or 27 wherein said transfer channel is counter doped to said secondconductivity type to a net doped concentration less than that of firstand second channel regions.
 37. A method as in claims 25, 26, or 27organized into a plurality of sectors, each sector comprising one ormore rows and organized such that erasure of all cells of a sector isperformed simultaneously.
 38. A method as in claims 25, 26, or 27organized as a virtual ground array.
 39. A method as in claims 25, 26,or 27 wherein said one of first or second floating gates in alternatecells in a given row are verified simultaneously.
 40. A method as inclaim 39 wherein an entire row is verified utilizing four verificationoperations.
 41. A method as in claims 25, 26, or 27 wherein said one offirst or second floating gates of alternate cells in a given row areprogrammed simultaneously by placing data associated with each memorycell to be programmed on its associated diffused line.
 42. A method asin claim 20 wherein an entire row is programmed utilizing four programoperations.
 43. A method as in claims 22, 23 or 24 wherein said steps offorming said first floating gate and said first control gate, and saidsecond floating gate and said second control gate comprising the stepsof: forming a plurality of polycrystalline silicon strips in a firstdirection above and insulated from said first and second channelregions; forming a layer of polycrystalline silicon above and insulatedfrom said plurality of polycrystalline silicon strips; and patterningsaid plurality of polycrystalline silicon strips and said layer ofpolycrystalline silicon into strips running in a second directiongenerally perpendicular to said first direction in order to form saidfirst and second floating gates and said first and second control gates.44. A method as in claims 25, 26, or 27 wherein said steps of formingsaid first floating gate and said first control gate, and said secondfloating gate and said second control gate comprising the steps of:forming a plurality of polycrystalline silicon strips in said seconddirection above and insulated from said first and second channelregions; forming a layer of polycrystalline silicon above and insulatedfrom said plurality of polycrystalline silicon strips; and patterningsaid plurality of polycrystalline silicon strips and said layer ofpolycrystalline silicon into strips running in said first direction inorder to form said first and second floating gates and said first andsecond control gates.
 45. A method as in claim 43 wherein said step ofpatterning said plurality of polycrystalline silicon strips and saidlayer of polycrystalline silicon is performed using the minimum featurelithographic width available in the fabrication process.
 46. A method asin claim 44 wherein said step of patterning said plurality ofpolycrystalline silicon strips and said layer of polycrystalline siliconis performed using the minimum feature lithographic width available inthe fabrication process.
 47. A method as in claims 22, 23, 24, 25, 26,or 27 wherein said step of forming said transfer channel region and saidsource and drain regions comprises the step of delineating said transferchannel region and said source and drain regions simultaneously.
 48. Amethod as in claim 47 wherein said step of simultaneously delineatingsaid transfer channel region and said source and drain regions isperformed utilizing the minimum lithographic space between featuresavailable in the fabrication process.
 49. A method as in claims 22, 23,24, 25, 26, or 27 which further comprises the step of forming a tunneloxide on only the edges of said first floating gate and said secondfloating gate adjacent to said transfer channel region.
 50. A method asin claims 25, 26, or 27 which further comprises the step of forming atunnel oxide on only the edges of said first floating gate and saidsecond floating gate adjacent to said transfer channel region to serveas said tunneling zones, comprising the steps of: forming a plurality ofpolycrystalline silicon strips; forming a second layer ofpolycrystalline silicon above and insulated from said first layer ofpolycrystalline silicon; patterning said second layer of polycrystallinesilicon to form said plurality of said first and second control gates;patterning said first layer of polycrystalline silicon to removeportions of said first layer of polycrystalline silicon between adjacentpairs of said first and second control gates; forming spacer dielectricon the exposed side walls of said first and second polycrystallinesilicon layers; removing exposed portions of said first polycrystallinesilicon layer; forming tunnel oxide on the exposed side walls of saidfirst polycrystalline silicon layer; and forming a third layer ofpolycrystalline silicon.
 51. A method as in claim 50 wherein a portionof said first and second channel regions adjacent said source regionsand drain regions, respectively, are doped to concentrations greaterthan that of the remaining portions of said channel regions prior tosaid step of forming spacer dielectric and said source and drain regionsare formed after said step of forming said spacer dielectric.
 52. Amemory array comprising a plurality of segments, each segment includinga subarray comprising: a plurality of adjacent bit lines running in afirst direction to form a corresponding plurality of columns; aplurality of steering lines running in said first direction; a pluralityof word lines running in a second direction generally perpendicular tosaid first direction to form a corresponding plurality of rows; and aplurality of memory cells, each memory cell being associated with theintersection of one of said bit lines and one of said word lines.
 53. Astructure as in claim 52 wherein said word lines serve as said eraselines.
 54. A structure as in claim 53 which includes one or moresectors, each sector containing one or more of said word lines and theircorresponding erase lines, each said sector containing a plurality ofmemory cells capable of being simultaneously erased.
 55. A structure asin claim 53 which includes one or more sectors, each sector containingone or more of said word lines which also serve as erase lines, eachsaid sector containing a plurality of memory cells capable of beingsimultaneously erased.
 56. A method as in claim 52 which furthercomprises the step of storing one of two or more logical states in saidmemory cell.
 57. A memory array as in claim 52 organized as a virtualground array.
 58. A memory array as in claim 52 which further comprises:a plurality of diffused lines running in said first direction, servingas said bit lines and forming source and drain regions of said memorycells, each memory cell having a first channel region located adjacentsaid source region and a second channel region located adjacent saiddrain region, and a transfer channel region located between its saidfirst and second channel regions; a plurality of first floating gates,each located above said first channel region of an associated one ofsaid memory cells; a plurality of second floating gates, each locatedabove said second channel region of an associated one of said memorycells; a plurality of first control gate lines, running in said firstdirection, each located above an associated set of said first floatinggates and serving as those of said steering lines associated with eachsaid first floating gate; a plurality of second control gate lines,running in said first direction, each located above an associated set ofsaid second floating gates and serving as those of said steering linesassociated with each said second floating gate; and a plurality of rowlines serving as said word lines, running in said second directiongenerally perpendicular to said first direction, forming a set of thirdcontrol gates above said transfer channel regions of each memory cell,overlying at least a portion of associated ones of said first and secondcontrol gates and serving as control gates of access transistors ofassociated memory cells, wherein each of said memory cells is associatedwith the intersection of one of said diffused lines and one of said rowlines, and wherein each memory cell includes a first tunnelling zoneformed between said first floating gate and said third control gate, andincluding one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said first floatinggate, and wherein each memory cell includes a second tunnelling zoneformed between said second floating gate and said third control gate,and including one or more of edges, side wall, corners of the top edge,portions of the top, and portions of the bottom of said second floatinggate.
 59. A memory array as in claim 58 wherein said one of first orsecond floating gates in alternate cells in a given row are verifiedsimultaneously.
 60. A memory array as in claim 59 wherein an entire rowis verified utilizing four verification operations.
 61. A memory arrayas in claim 58 wherein alternate cells in a given row are programmedsimultaneously by placing data associated with each memory cell to beprogrammed on its associated bit line.
 62. A memory array as in claim 61wherein an entire row is programmed utilizing four program operations.63. A structure as in claims 1, 2, 3, 4, 5, 6, or 52 which furthercomprises steering bias circuitry capable of providing steering biasvoltage levels less than zero.